The present invention generally relates to conductive plug forming methods, and more particularly to a conductive plug forming method in which a plug is formed in a via hole by applying an energy beam to melt a metal layer which is deposited in the vicinity of the via hole.
When a metal layer for interconnection is deposited on a surface which is not perfectly planar by a vapor deposition or a sputtering process, it is known that the step coverage of the metal layer is generally poor. The deposition of the metal layer is poor especially at an inner surface of a via hole such as a contact hole and a through hole. As the integration density of semiconductor devices increases and the device count per chip increases, the interconnection become extremely fine and the via hole also becomes extremely fine. As a result, it becomes more and more difficult to ensure positive deposition of the metal, and it is extremely difficult to form a satisfactory interconnection by simply depositing the metal layer by the vapor deposition or sputtering processes.
On the other hand, there is a method of irradiating a pulse laser beam on the metal layer to carry out a planarization process step. The inside of the via, hole is filled by the metal by this planarization step, but it is difficult to control the thickness of the metal layer and keep it uniform when the metal layer is not perfectly planar. For this reason, inconveniences are introduced when the metal layer is etched in a latter process.
Accordingly, a method of filling a metal inside the via hole before depositing a metal layer thereon was proposed in a Japanese Laid-Open Patent Application No.58-115835.
However, various kinds of via holes exist in semiconductor devices and the size and depth of these via holes are quite different depending on the use of the via holes. As a result, it is extremely difficult to satisfactorily fill the inside of each of the various kinds of via holes.